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SC420
POWER MANAGEMENT POWER MANAGEMENT Description
The SC420 is a cost effective Dual MOSFET Driver, incorporating Semtech's patented Combi-SenseTM technology, designed for switching High and Low side Power MOSFETs in Step-down Switching regulators. A 20ns max propagation delay from input transition to the gate of the power FET's guarantees operation at high switching frequencies. Internal overlap protection circuit prevents shoot-through from Vin to GND in the main and synchronous MOSFETs. High current drive capability (2A peak) allows fast switching, thus reducing switching losses at high (up to 1.5MHz) frequencies without causing thermal stress on the driver.
High Speed, Combi-Sense , Synchronous Power MOSFET Driver for Mobile Applications
TM
TARGET
Features
u u u u u u u u u
High efficiency Shutdown mode for increased power saving Tri-state capability Fast rise and fall times (15ns typical with 3000pF load) 5V gate drive Ultra-low (<20ns) propagation delay (BG going low) Adaptive and programmable non-overlapping gate drives provide shoot-through protection Floating top drive switches up to 27V High frequency (to 1.5 MHz) operation allows use of small inductors and low cost ceramic capacitors Under-voltage lockout Low quiescent current MLP packaging provides superior thermal performance in a small footprint
u u The high voltage CMOS process allows operation up to u
27 Volts, making the SC420 suitable for adaptor powered applications. Under-voltage-lockout and over-temperature shutdown features are included for proper and safe operation. The SC420 is offered in a space saving MLP-12 package.
Applications Conceptual Application Circuit
VIN2
u High efficiency portable and notebook computers u Battery powered applications
VIN
D1
M1 VIN VIN2 VIN TG PWM CO BST
FB
Combi-SenseTM Controller IC
SC420
EN DRN BG CDELAY VPN
CBST
L1
VOUT
EN
GND
CS- CS+
M2 RVPN CVPN CDELAY
CL
Figure 1 Rev 4. December 2003 1 United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter VIN2 Supply Voltage BST to PGND BST to DRN DRN to PGND
Symbol VIN2
Conditions
Min
Max 30 40 VIN + 2
Units V V V V
tPULSE<100ns static
-5 -2 -2 - 0.3
34 30 BST + 0.3 VIN + 0.3 30 7
TG BG VPN to PGND VIN to PGND EN, CO, CDELAY Continuous Power Dissipation PD Tamb = 25 oC,TJ = 125 oC Tcase = 25 oC, TJ = 125oC Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient (1) Operating Junction Temperature Range Storange Temperature Range Peak IR Reflow (10-40 sec) JC JA TJ TSTG TIRreflow VPN VIN
V V V V V W
- 0.3
VIN + 0.3 0.66 2.56 3 48
o
C/W C/W
o
o
- 40 - 65
125 150 240
C C C
o
o
Note: (1) Performance when used according to manufacturing guidelines, refer to Applications Information section for more information (2) Specification refers to application circuit in Figure 1
Electrical Characteristics
Unless specified: TA = 25C; VIN = 5V; 0V < VDRN < 25V
Parameter Power Supply Supply Voltage
Symbol
Conditions
Min
Typ
Max
Units
V IN V IN2
4.75
5
6 27
V V mA mA
Quiescent Current, Operating (static) Quiescent Current, Tri-state Quiescent Current, Shutdown
(1) Guaranteed by design (c) 2003 Semtech Corp.
IQ op IQ ts IQ sd
CO = 0V, EN > 2.2V CO floating CO = 0V, EN = 0V
2
2.3 2.3 0.2 20
A
United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25C; VIN = 5V; 0V < VDRN < 25V
Parameter Under Voltage Lockout Start Threshold (ramping up) Hysteresis Under-Voltage Lockout Time Delay VIN ramping up (1) VIN ramping down EN High Level Input Voltage Low Level Input Voltage CO High Level Input Voltage Low Level Input Voltage Tri-state Level Thermal Shutdown Over Temperature Trip Point
(1) (1)
Symbol
Conditions
Min
Typ
Max
Units
VIN Vhys
4.1 100
4.3 200
4.55 350
V mV
tpdhUVLO tpdLUVLO
2 2
s s
VIH VIL
2.0 0.8
V V
2.0 0.8 CO floating 1.0 1.9
V V V
TOTP THYST
165 10
o
C C
Hysteresis (1) High Side Driver (TG) Peak Output Current Output Resistance
(1)
o
IPKH RSRC_TG RSINK_TG I= 100mA VBST-VDRN = 5V VBST-VDRN = 5V CL = 3nF,VBST - VDRN = 5V
1.3 3.4
A
1.1 15 15 24 24 ns ns
Rise Time (1) Fall Time
(1)
trTG tfTG
(1) Guaranteed by design (c) 2003 Semtech Corp. 3 United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25C; VIN = 5V; 0V < VDRN < 25V
Parameter Propagation Delay, TG Going High (1) Propagation Delay, TG Going Low (1) Low-Side Driver (BG) Peak Output Current Output Resistance
(1)
Symbol tpdhTG tpdlTG
Conditions CTG = 3nF,BG = 0V CTG = 3nF,DRN = 0V
Min 20 15
Typ
Max
Units ns ns
IPKL RSRC_BG I = 100mA RSINK_BG
2.0 3.4
A
0.9 CBG = 3nF CBG = 3nF C BG=3nF, DRN = 0V CBG = 3nF 15 10 12 15 24 17 ns ns ns ns
Rise Time (1) Fall Time (1) Propagation Delay,BG Going High (1) Propagation Delay,BG Going Low (1) Shoot-thru Protection (CDELAY) Shoot-thru Protection Delay Time (1) Programmed Delay CDELAY charge current Virtual Phase Node (VPN) Output Resistance
trBG tfBG tpdhBG tpdlBG
tspd
CCDELAY open
20 1
ns ns/pF A
ICDELAY
500
RSRC_VPN RSINK_VPN
65 90 600
Leakage
ILEAK_VPN
nA
(1) Guaranteed by design (c) 2003 Semtech Corp. 4 United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Device (1) SC420IMLTR Package MLP-12 Temp Range (TJ) -40 to 125C
PGND
12
N.C. DRN
11
10
Note: (1) Only available in tape and reel packaging. A reel contains 3000 devices.
9 8 7
TG BST CO
1 2 3
BG VIN CDELAY
(2) This device is ESD sensitive. Use of standard ESD
handling precautions is required.
4
5
6
(MLP-12)
Pin Descriptions
Pin # 1 2 3 4 5 6 Pin Name TG BST CO VIN2 EN VPN Pin Function Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1F and 1F (ceramic). Logic level PWM input signal to the SC420 supplied by external controller. Input power (VBAT) to the DC/DC converter. Used as supply reference for internal Combi-Sense TM circuitry. Connect as close as possible to Drain of TOP switching MOSFET. Active high logic level input signal. A logic High enables TG and BG switching. A low level disables outputs and reduces quiescent current to IQ SD Virtual Phase Node. Connect an RC between this pin and the output sense point to Enable CombiSense TM operation.
7
The capacitance connected between this pin and GND sets the additional propagation delay for BG CDELAY going low to TG going high. Total propagation delay =20ns + 1ns/pF. If no capacitor is connected, the propragation delay = 20ns. VIN BG PGND N.C. DRN Input supply for the bottom drive and the Logic. A 1F-10F Ceramic Capacitor must be connected from this pin to PGND, placed less than 0.5" from SC420. Output drive for the synchronous (bottom) MOSFET. Ground. Keep this pin close to the synchronous MOSFETs source. No Connect This pin connects to the junction of the switching and synchronous MOSFETs . This pin can be subjected to a -2V minimum relative to PGND without affecting operation.
5 United States Patent No. 6,441,597 www.semtech.com
VIN2
VPN
EN
8 9 10 11 12
(c) 2003 Semtech Corp.
SC420
POWER MANAGEMENT Block Diagram
VIN2
VIN
VIN
VPN
VIN
VIN
VIN
BST TG CDELAY
STEERING/ LOGIC OVERLAP PROTECTION
DRN
VIN
CO
BG
Vref
PGND
EN
BANDGAP Vref
Timing Diagram
CO
tpdl
TG
tfTG
tpdhTG
tr TG
TG
tpdh BG tr BG tpdl BG tf BG tspd
BG
tri - state
tri - state
VPN
(c) 2003 Semtech Corp.
6
United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT Applications Information
Combi-Sense (Lossless current sense) The Combi-Sense is a way to sense the output current on a combination of power devices. There is no sense resistor and the current is sensed on: Top MOSFET, bottom MOSFET and output inductor. An internal phase node VPN sends a signal which is integrated by the Combi-Sense network. This network consists of a resistor and capacitor in series, connected between VPN and the DRN pins. The resulting signal is large, clean and not duty cycle sensitive. It can be used directly for close loop current mode control and current limit. Fast Switching Drives As the switching frequency of PWM controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP MOSFET) and reduce dead-time (BOTTOM MOSFET) losses. While low Rds_On MOSFET's present a power saving, the MOSFETs die area is larger and the effective input capacitance of the MOSFET is increased. Often a 50% decrease in Rds_On doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a suboptimum driver. While discrete solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and costly. The SC420 presents a total solution for the high-speed, high power density applications. Wide input supply range of 4.5V25V allows use in battery powered applications, new high voltage, distributed power supplies. Shoot Through Protection The control input (CO) to the SC420 is typically supplied by a PWM controller that regulates the power supply output. The timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the
(c) 2003 Semtech Corp. 7
input supply and ground, a shoot-through condition during which both the top and bottom FET's could be on momentarily. The top FET is also prevented from turning on until the bottom FET is off. The top FET turn-on delay is internally set to 20ns (typical) and may be programmably extended by an external capacitor on the Cdelay pin, the delay is increased by 1ns/pf. The EN (enable) pin may be used to turn both TG and BG drives off. This lowers power consumption by reducing the quiescent current draw of the SC420 to IQsd. Tri-State If the CO pin is undriven it will float to an internally defined voltage of 1.4V. This will switch the TG and BG pins low and also tri-states the VPN node. Over Temperature Shutdown The SC420 will shutdown by pulling both driver's low if its junction temperature, TJ, exceeds 165C. The drivers will resume operation when TJ declines below 155oC. Layout Guidelines As with any high speed , high current, switching regulator circuit, proper layout is critical in achieving optimum performance of the SC420. The Combi-SenseTM Controller Evaluation board schematic shows a three-phase synchronous design with all surface mountable components. Tight placement and short, wide traces must be used in layout of The gate drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the boost supply and adding it to the phase node (DRN) voltage. Since the bootstrap capacitor supplies the charge to the top gate, it must be less than 0.5in away from the SC420. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. Supply Voltage The SC420 can operate from 4.75V to 6V. The VIN pin bypass capacitor must also be less than 0.5in away from the SC420. The ground node of this capacitor, the SC420 PGND pin and the Source of the bottom FET must
United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT Applications Information (Cont.)
be very close to each other, preferably with common PCB copper land with multiple vias to the ground plane (if used). The parallel Schottky (if used) must be physically next to the Bottom FET's drain and source pins. Any trace or lead inductance in these connections will drive current way from the Schottky and allow it to flow through the FET's Body diode, thus reducing efficiency. Preventing Inadvertent Bottom FET Turn-on At high VIN2 input voltages, (12V and greater) a fast turnon of the top FET creates a positive going spike on the Bottom FET's gate through the Miller capacitance, Crss of the bottom FET. The voltage appearing on the gate due to this spike is:
VSPIKE = Vin * Crss (Crss + Ciss )
mined by:
Fring = 1 1 = ( 2 * Sqrt ( LST * Coss ) 2 LST * COSS
-Where: Lst = The effective stray inductance of the top FET added to trace inductance of the connection between top FET's source and the bottom FET's drain added to the trace resistance of the bottom FET's ground connection. COSS = Drain to source capacitance of bottom FET. If there is a Schottky used, the capacitance of the Schottky is added to this value. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. On the SC420, the drain node, DRN, can go as far as 2V below ground without affecting operation or sustaining damage. The ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 10002000pf, in parallel with Coss of the bottom FET will often eliminate the EMI issue. Prevent Driver Overvoltage The negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. This is of special importance if higher boost voltages are used. If the phase node negative spikes are too large, the voltage on the boost capacitor could exceed device's absolute maximum rating of 7V. To eliminate the effect of the ringing on the boost capacitor voltage, place a 4.7 - 10 Ohm resistor between boost Schottky diode and VIN to filter the negative spikes on DRN Pin. Alternately, a Silicon diode, such as the commonly available 1N4148 can substitute for the Schottky diode and eliminate the need for the series resistor. Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of surface mount MOSFETs, while increasing thermal resistance, will reduce lead inductance as well as radiated EMI.
8 United States Patent No. 6,441,597 www.semtech.com
Where Ciss is the input gate capacitance of the bottom FET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors, since dV/dT and thus the effective frequency is very high. If the BG pin of the SC420 is very close to the bottom FET, Vspike will be reduced depending on trace inductance, rate of rise of current, etc. A capacitor may be added from the gate of the Bottom FET to its source, preferably less than 0.5in away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage. The bottom MOSFET must be selected with attention paid to the Crss/Ciss ratio. A low ratio reduces the Miller feedback and thus reduces Vspike. Also MOSFETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. A zero ohm bottom FET gate resistor will obviously help keeping the gate voltage low during off time. Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. It does this at the expense of increased switching times (and switching losses) for the top FET. The top MOSFET source must be close to the bottom MOSFET drain to prevent ringing and the possibility of the phase node going negative. This frequency is deter(c) 2003 Semtech Corp.
SC420
POWER MANAGEMENT Applications Information (Cont.)
Start-up Sequencing Proper sequencing of the Combi-SenseTM Controller and SC420 driver during both start-up and shut-down is very important. In general, the design must ensure that the driver powers up (during start-up) before the controller does, and that the driver powers down last during shutdown. This ensures that the driver will never puts out gate drive pulses which are not well-controlled, a situation that can lead to MOSFET damage. In general it is recommended that the Vcc's for the CombiSenseTM Controller and SC420 be connected to the same (5V) supply. If the EN controls are not used (tied high) then the UVLO settings for the controller and driver will guarantee the proper sequencing (the SC420 maximum UVLO value is guaranteed to be lower than the CombiSenseTM Controller minimum UVLO value). For absolute guarantee of proper sequencing it is recommended that the EN controls be used as shown in the following block diagram. With this arrangement the delayed PWRGD signal from the VccVID regulator is used to enable both ICs. The Soft-Start time established for the controller ensures it will come up well after the SC420. During power-down de-assertion of VID_PWRGD will ensure simultaneous disabling of the Combi-SenseTM Controller and SC420. Manufacturing Guidelines Detailed information on manufacturing and rework of PCBs using the MLP package can be found in the MLP application note "Comprehensive User's Guide - Micro Lead Frame Package" dated April 2002. Please contact your local Semtech representative to obtain a copy of this application note.
V5
SC1403
SYS_PWRGD
V3
VR_ON CO VccVID Regulator SC400 VID_PWRGD EN EN SC420
Vcc-CORE
VccPWRGD
(c) 2003 Semtech Corp.
9
United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT
TG, BG, and DRN Waveforms
VIN2 = 10V
Zoom in on TG, BG, and AUX Rising
VIN2 = 10V
(c) 2003 Semtech Corp.
10
United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT
DRN and AUX Timing
VIN2 = 10V
(c) 2003 Semtech Corp.
11
United States Patent No. 6,441,597 www.semtech.com
SC420
POWER MANAGEMENT Outline Drawing - MLP-12
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
(c) 2003 Semtech Corp.
12
United States Patent No. 6,441,597 www.semtech.com

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